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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 august 1993 integrated circuits saa2521 masking threshold processor for mpeg layer 1 audio compression applications
august 1993 2 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 features stereo or 2-channel mono encoding status may be read continuously microcontroller interface i 2 s-interfaces allocation algorithm including optional emphasis correction (for 44.1 khz) reduced power consumption 4 v nominal operating voltage capability. general description the saa2521 performs the adaptive allocation and scaling function for calculating the masking thresholds and sub-band sample accuracy in mpeg layer 1 applications. the saa2521 is intended for use in conjunction with the stereo filter codec saa2520. ordering information note 1. sot205-1; 1996 august 23. extended type number package pins pin position material code SAA2521GP 44 qfp plastic sot205ag (1)
august 1993 3 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.1 block diagram. handbook, full pagewidth interface interface compensation delay control allocation and scaling calculation 33 39 34 fs256 fdaf fdac mlb137 lt interface ltdata clk24 ltdatac saa2521 32 scl 14,24,40 v dd ltcnt1c ltcnt0c ltenc ltclkc 6,25,44 v ss nodone resol0 fdir resol1 freset fsync ltcnt1 ltcnt0 ltena reset pwrdwn 20 21 22 37 36 35 5 1 2 3 4 26 23 30 11 7 8 9 10 ltclk sws 31 scale 38 test3 15 test4 16
august 1993 4 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 saa2521 fdac scl sws pwrdwn test10 test9 test8 clk24 v ss v dd reset v ss n.c. n.c. v dd fs256 scale fdir freset fsync fdaf n.c. test1 test2 v dd test3 test4 test5 test6 test7 nodone resol0 resol1 ltcnt1 ltcnt0 ltena ltclk ltdata v ss ltcnt1c ltcnt0c ltenc ltclkc ltdatac mlb136 fig.3 mpeg codec system data flow diagram. handbook, full pagewidth mlb138 microcontroller adc/dac saa2520 and saa2521 digital audio interface control system micro interface power down reset mpeg source/ receiver mpeg interface audio source audio amplifier
august 1993 5 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 pinning symbol pin description type ltcnt1 1 mode control 1, microcontroller interface input i ltcnt0 2 mode control 0, microcontroller interface input i ltena 3 enable microcontroller interface input i ltclk 4 bit clock microcontroller interface input i ltdata 5 data, microcontroller interface (3-state inputs/outputs) i/o v ss 6 supply ground (0 v) ltcnt1c 7 control 1; microcomputer interface o ltcnt0c 8 control 0; microcomputer interface o ltenc 9 enable microcontroller interface o ltclkc 10 bit clock; microcontroller interface o ltdatac 11 data; microcontroller interface, (3-state inputs/outputs) i/o test1 12 test output; do not connect test2 13 test output; do not connect v dd 14 positive supply voltage ( + 5 v) test3 15 test mode input; to be connected to v dd test4 16 test mode input; to be connected to v dd test5 17 test input; to be connected to v ss test6 18 test input; to be connected to v ss test7 19 test input; to be connected to v ss nodone 20 no done state selection input i resol0 21 resolution selection 0 input i resol1 22 resolution selection 1 input i reset 23 active high reset input i v dd 24 positive supply voltage ( + 5 v) v ss 25 supply ground (0 v) clk24 26 24.576 mhz processing clock input i test8 27 test input; to be connected to v ss test9 28 test input; to be connected to v ss test10 29 test input; to be connected to v ss pwrdwn 30 power-down input i sws 31 word selection input; (filtered) - i 2 s-interface i scl 32 bit clock input; (filtered) - i 2 s-interface i fdac 33 ?ltered data (filtered) - i 2 s-interface (3-state inputs/outputs) i/o fdaf 34 ?ltered data (filtered) - i 2 s-interface (3-state inputs/outputs) i/o fsync 35 sub-band synchronization on (filtered) - i 2 s-interface, input i freset 36 reset signal input from saa2520 i fdir 37 direction of the i 2 s-interface; input i scale 38 scale factor index select (note 1) i fs256 39 system clock input; sample frequency 256 i v dd 40 positive supply voltage ( + 5 v)
august 1993 6 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 note to the pinning description 1. the scale input must be set low for use with the saa2521. n.c. 41 not connected n.c. 42 not connected n.c. 43 not connected v ss 44 supply ground (0 v) symbol pin description type functional description coding system this efficient mpeg audio encoder is used in conjunction with the saa2520 filter codec (bit rates of 384, 256, 192 and 128 k bits/s). the encoder utilizes a system producing sub-band samples from an incoming digital audio signal. this relies upon the audibility of signals above a given level and upon high amplitude signals masking those of lower amplitude. although each sub-band signal is of approximately 750 hz bandwidth, it possesses considerable overlap with those adjacent to it. during the process of encoding, the masking threshold processor analyses the broadband audio signal at sampling frequency f s by splitting it into 32 sub-band signals at a sampling frequency (f s /32). the coded signal consists of frames conveying the information corresponding to the sub-band samples. these also include a synchronization pattern identifying the start of each new frame. the allocation information for the 32 sub-bands is transferred as 4-bit values. if the amplitude of a sub-band signal is below the masking threshold it will be omitted from the coded signal. the duration of a mpeg frame depends upon sampling frequency and is adjusted to 384 divided by f s . adaptive allocation and scaling the coding system calculates the masking power of the sub-band signals and adds the masking threshold. sub-band signals with power below this threshold denote information to be discarded. non-masked signals are coded using floating point notation in which a mantissa corresponds in length to the difference between peak power and masking threshold. the process is repeated for every mpeg frame and is known as the adaptive allocation of the available capacity. encoding mode signal fdir sets the data flow direction on the filtered-i 2 s-interface. in the encoding mode (fdir low) the device will accept samples from fdaf. these will be delayed by a number of sample periods depending upon the setting of the scale input. in the instance of operation with the saa2520 (scale = logic 0) this delay will be 480 sws periods. this will ensure alignment of the data with the computed allocations. after the delay the samples will be presented on fdac (pin 33). the circuit also performs all the calculations required to build the allocation table which is used in the codec (saa2520). when used with the saa2520 the calculated scale factor indices are sent via the lt interface. these operations are performed for every frame of the sub-band codec. in order to synchronize with the codec and utilize the correct tables for the calculations the saa2521 frequently requests the status of the codec. it monitors the bit-rate, sample frequency, operation mode and the emphasis information and uses the 'ready to receive' bit of the codec to determine the moment of the transfer of allocation information. decoding mode in the decoding mode (fdir high) the saa2521 will take samples from fdac which will be presented on the fdaf after a delay of 160 sws periods. the lt interface between microcontroller and codec (saa2520) will only be affected by the 'ready to receive' bit from the codec (saa2520).
august 1993 7 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 microcontroller interface operation information on the interface between microcontroller and codec (saa2520) will flow in a regular sequence synchronized with the codec (saa2520): - with every fsync the saa2521 will read the status of the codec (saa2520) - following the calculation of the allocation and scale factors the saa2521 will send the ?rst allocation information unit (16-bits). it will then continuously read the codec (saa2520) status to ascertain when it is able to receive further allocation information units. when the transfer of these units is complete the saa2521 will send settings and (for scale = logic 0) scale factor indices. - the extended settings will be sent to the codec as soon as possible after reception from the microcontroller. the microcontroller communicates with the saa2521 in a similar fashion: - status can be read continuously. the saa2521 will output a copy of the codec (saa2520) status on the ltdata line except for the 'ready to receive' bits which are generated by the saa2521. these indicate whether the saa2521 is ready to receive the next settings or extended settings. - settings can be sent following every occasion that the 'ready to receive' bit 's' changes to logic 1. - extended settings can be sent following each occasion that the 'ready to receive' bit 'e' changes to logic 1. mode control operation is controlled by the freset and fdir signals. freset causes a general reset. the fdir signal is sampled at the falling edge of the freset signal to determine the operation mode: fig.4 shows the timing diagram for freset and fdir. resolution selection the (saa2521) is designed for operation with input devices (adcs) which may possess a different sample resolution capability, i.e. audio sample inputs into the sub-band filters. pins resol0 and resol1 (respectively pins 21 and 22) may be utilized to adjust the allocation information calculation to the resolution of the samples. with the instance of pin 20 (nodone) being high, all available bits in the bit-pool will be allocated. if nodone is low, no bits will be allocated to the sub-bands with energy levels below the theoretical threshold for the selected resolution. fdir = logic 1 decoding mode, saa2521 in feed-through mode fdir = 0 encoding mode, saa2521 in calculation mode fig.4 timing: freset and fdir. t rh > 5t clk24 = 210 ns (for clk24 = 24.576 mhz) min. time freset high t sd < 0 ns min. set-up time fdir to freset = low mbc123 - 1 freset fdir t rh t sud
august 1993 8 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 power-down mode switching when the potential on the reset pin (pin 23) is held high for at least 5t clk24 clock periods, the device will be reset after which it will operate in its decoding mode. the power-down mode is activated when the pwrdwn pin (pin 30) is held high. the 3-state buffers will be set to a high impedance while the normal outputs will retain the state attained prior to this mode being entered. this mode can only be used if other associated circuits react accordingly. the power-down mode is de-activated by a reset action. fig.5 shows the operation for the power-down mode switching. table 1 resolution selection. resol1 resol0 resolution 0 0 16-bits 0 1 18-bits 1 0 14-bits 1 1 15-bits fig.5 power-down mode switching. t rh > 5t clk24 = 210 ns (for clk24 = 24.576 mhz) minimum time reset high mea659 - 1 sleep mode active pwrdwn reset t rh
august 1993 9 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.6 format for transferring filtered data. mbc149 - 1 left 32 bits right 7 bits 1 210 2 3 2 2 2 1 2 0 msb lsb 2 3 2 2 2 1 2 0 msb channel sws scl fda bit : fig.7 fsync related to sws 0 data transfer period. mbc126 - 2 channel sws lrllllll rrrrrr fsync sub-band 31 0 1 31 0 1
august 1993 10 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 table 2 the (filtered) - i 2 s-interface. table 3 the (filtered) - i 2 s-interface. sws input word selection f s scl input bit clock 64 f s fdaf bi-directional ?ltered data to/from the ?lter section of saa2520 fdac bi-directional ?ltered data to/from the codec section of saa2520 fsync input ?lter synchronization f s /32 freset input reset fdir input filtered - i 2 s-interface direction of data ?ow (filtered) - i 2 s-interfaces interfaces with the sub-band filter and codec (saa2520) consist of the following signals. fig.6 shows the format for transferring filtered data. f s 256 must be provided as system clock. this frequency is used by the interfaces with the saa2520. the frequency of the sws signal (pin 31) is equal to the sample frequency f s . bit clock scl (pin 32) is 64 times the sample frequency; thus each sws period contains 64 data bits, 48 of which are actually used in data transfer. the half period during which sws is logic 0 is used to transfer left-channel information while that during which it is 1 permits transfer of right-channel data. the 24-bit samples are transferred with the most significant bit first. this bit is transferred during the bit clock period, one bit time after the change in sws. fsync signal is provided for the purposes of synchronization and indicates the portion of the sws period during which the samples of sub-band 0 are transferred. fig.7 shows the relationship between fsync and the sws 0 data transfer period.
august 1993 11 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.8 (filtered) - i 2 s-interface timing. t w1 3 3t minimum time high impedance to fda enabled t w2 3 2t + 35 ns maximum time fda enabled to high impedance output applies to fdaf and fdac in the output mode. input applies to fdaf and fdac in the input mode, sws and fsync. t = one f s 256 cycle time t ch 3 t + 35 ns minimum high time scl t cl 3 t + 35 ns minimum low time scl t d3 3 2t - 10 ns hold time output after scl high t d4 3t + 60 ns delay time output after scl high t s1 3 20 ns set-up time input before scl high t h1 3 t + 35 ns hold time input after scl high mbc127 - 2 t ch 4t t cl t su1 t h1 t d4 t d3 scl output input mea692 - 1 fdir fda t w1 t w2 high z high z
august 1993 12 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 table 4 saa2521 interface with microcontroller. ltclk input bitclock ltdata bi-directional data ltcnt0 input control line 0 ltcnt1 input control line 1 ltena input enable table 5 saa2521 interface with saa2520. ltclkc output bit clock ltdatac bi-directional data ltcnt0c output control line 0 ltcnt1c output control line 1 ltenc output enable table 6 saa2521 interface control lines functions. ltcnt1(c) ltcnt0(c) mode from to transfer of 0 0 extended settings microcontroller saa2520 8-bits 0 1 allocation (see note) saa2521 saa2520 16/48 16-bits 1 0 settings microcontroller saa2520 16-bits 1 1 status codec microcontroller 8 or 16-bits microcontroller interface two microcontroller interfaces are provided; one for connection to the microcontroller interface of the saa2520, the other to connect to the system controller. information is conveyed via the saa2521 which executes monitoring and extracts signals (e.g. settings and synchronization) essential to its operation. additionally it also sends allocation information to the saa2520. however, the saa2521 does not monitor the external settings bits from the microcontroller (see extended settings). the saa2521 is a slave on the interface with the microcontroller which is active only when the enable signal ltena (pin 3) is logic 1. this permits connection of this interface to other devices. only the enable signal is not common to all devices. saa2521 is master on the interface with the saa2520 and provides all signals with the exception of the data in the instance of status transfer from saa2520 to saa2521. information conveyed via these interfaces is transferred in 8 or 16-bit serial units with the type of information designated by the control lines (ltcnt1(c) and ltcnt0(c)). a transfer of information begins when the master sets the control lines for the required action. it then sets the ltena/c line to logic 1. once this signal is established the slave determines the kind of action required and prepares for the transfer of data. when the master supplies the ltclk/c signal, data is transferred either to or from the slave in units of 8-bits; the least significant bit is always transferred first. a transfer of 16-bits is made in two, 8-bit units with the most significant 8-bit unit first. in between the two 8-bit units the ltena/c signal remains logic 1. fig.9 shows an example of information transfer via saa2521 interfaces. note to table 6 this mode only on the interface between saa2521 and saa2520. if scale = logic 1 then 16 16-bits if scale = logic 0 then 48 16-bits
august 1993 13 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.9 example of information transfer via saa2521 interfaces. mbc128 01234567 ltena/c ltcnt0(c)/1(c) ltclk(c) ltdata(c) fig.10 extended settings (ltcnt1 and ltcnt0) refer to the saa2520 description for the meaning of these bits as they pass saa2521 unchanged. mbc129 e0 e1 e2 e3 e4 e5 e6 e7 ltena/c ltclk(c) ltdata(c) ltcnt0(c)/1(c)
august 1993 14 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 extended settings (ltcnt1(c) = logic 0, ltcnt0(c) = logic 0) eight information bits, generated by the microcontroller, are transferred in this mode. the saa2521 will transfer these bits to the saa2520 as soon as possible but does not monitor this information. fig.10 shows the relationship of the extended settings. allocation and scaling information (ltcnt1c = logic 0, ltcnt0c = logic 1) in the encoding mode (fdir = logic 0) the saa2521 will transfer allocation information to the saa2520. this will occur once for every saa2520 frame. the information will consist of 16 transfers each of 16-bits. to synchronize the saa2521 operation with that of the saa2520, following the first 16-bit transfer of allocation data the saa2521 checks the saa2520 status to ensure it is ready to receive the remainder of the allocation information. transfer of allocation data is completed by sending settings. between 16-bit transfers the ltenc line returns to 0 as shown in fig.11. fig.12 shows the order in which the bits occur on the interface during allocation information transfer. the 4-bit sub-band allocation unit contains the number of bits allocated to the sub-band minus 1. a value of 0000 indicates no bits allocated to that sub-band. fig.11 ltenc behaviour for 16-bit transfers. mbc130 ltenc ltclkc 16 bits 16 bits table 7 allocation and scaling information. table 8 allocation and scaling information. msb bits lsb channel sub-band a15 - a14 - a13 - a12 l 2 * count a11 - a10 - a9 - a8 r 2 * count a7 - a6 - a5 - a4 l (2 * count) + 1 a3 - a2 - a1 - a0 r (2 * count) + 1 msb bits lsb channel contents sl15 - sl14 - --- 00 sl13 - sl12 - sl11 - sl10 - sl9 - sl8 l scale factor (count) sl7 - sl6 --- 00 sl5 - sl4 - sl3 - sl2 - sl1 - sl0 r scale factor(count)
august 1993 15 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 with stereo encoding, left and right channels are designated l and r. this changes to channels i or ii for 2-channel mono mode. if scale = logic 0 the transfer of allocation information will be followed by the transfer of scale factors. each 16-bit transfer contains two scale factor indices. algorithm showing the process of information transfer: count: = logic 0 send allocation (count) repeat read status until ready-to-receive for count: = 1 to 15 do send allocation (count) send settings if scale = logic 0 then for count; = logic 0 to 31 do send scale factors (count) fig.12 order of interface bits during allocation information transfer. mea691 ltena/c ltclk(c) ltdata(c) bit : a or sl : 8 9 1 1 1 1 1 01234 01234567 1 5 ltcnt0(c)/1(c)
august 1993 16 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 settings (ltcnt1(c) = logic 1, ltcnt0(c) = logic 0) without using the information, the saa2521 transfers microcontroller settings to the saa2520. prior to sending settings, the microcontroller would utilize the saa2521 status readings to ensure its readiness to accept and convey the data. following reception of the settings the saa2521 will cause the ready-to-receive bit to be logic 0 until the settings have been sent to the saa2520. the microcontroller can only send this data when this bit is logic 1. fig.13 shows the order of the bits on the interface. table 9 microprocessor settings applied to the saa2520 via the saa2521. msb bits lsb name function valid in s15 - s14 - s13 - s12 bitrate index bitrate indication encode s11 - s10 sample frequency 44.1, 48 or 32 khz indic. encode s9 decode 1 - decode; 0 - encode enc/dec s8 ext 256f s 1 - ext; 0 - int enc/dec s7 2-ch mono 1 - 2 ch mono; 0 - stereo encode s6 mute 1 - mute; 0 - no mute enc/dec s5 not used - enc/dec s4 ch i 1 - ch i; 0 - ch ii decode s3 - s2 tr0 - tr1 transparent bits encode s1 - s0 emphasis emphasis indication encode fig.13 the order of bits on the interface. mbc132 ltena/c ltclk(c) ltdata(c) bit : s : 8911111 01234 01234567 1 5 ltcnt0(c)/1(c)
august 1993 17 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 status (ltcnt1(c) = logic 1, ltcnt0(c) = logic 1) the saa2520 and saa2521 operation may be checked by reading these bits. all, except the ready-to-receive bits, are generated by the saa2520. the bit rate index indicates the bit rate of the sub-band signal in units of 32 kbits/s. the saa2521 is designed for bit rates of 384, 256, 192 and 128 kbits/s only. with emphasis activated (s1 = t1 = 0 and s0 = t0 = 1) only bit rates 384 and 256 kbits/s can be used. a ready-to-receive s or e indicates whether or not the saa2521 can receive new settings or extended settings respectively from the microcontroller and should be checked prior to sending new information. the saa2521 can only be used to encode stereo (mode 00) signals and 2-channel mono (mode 10) signals. during the decoding mode this bit indicates if the operation of the saa2520 is in synchronization with the mpeg coded signal. should this not be the case the saa2520 cannot perform the decoding. clkok indicates whether or not the f s 256 clock corresponds with the specified sample frequency. emphasis indication may be used to apply correct de-emphasis. during the encoding 50 / 15 m s mode the saa2521 will correct the calculated allocation if emphasis is applied for a 44.1 khz sampling frequency. table 10 order of saa2520 bits as they appear on the interface (see also fig.14). msb bits lsb name function valid in t15 - t14 - t13 - t12 bitrate index bitrate indication enc/dec t11 - t10 sample frequency 44.1, 48 or 32 khz indic. enc/dec t9 ready-to-rec s 1 - ready; 0 - not ready enc/dec t8 ready-to-rec e 1 - ready; 0 - not ready enc/dec t7 - t6 mode sub-band signal mode id enc/dec t5 sync synchronization indic. dec t4 clkok 1 - ok; 0 - not ok enc/dec t3 - t2 tr0 - tr1 transparent bits enc/dec t1 - t0 emphasis emphasis indication enc/dec
august 1993 18 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.14 order of appearance of bits on the interface. mbc133 ltena/c ltclk(c) ltdata(c) bit : t : 8911111 01234 01234567 1 5 ltcnt0(c)/1(c) sample frequency indication. mode identi?cation. msb lsb 00 44.1 khz default value 01 48 khz 10 32 khz 11 -- do not use msb lsb mode output 00 stereo l and r 01 joint stereo l and r 10 2 - channel mono i or ii as selected 11 1 - channel mono mono, no selection frequency range limitation in encode mode the frequency range will be limited at lower rates. this is implemented by making the samples of higher frequency sub-bands equal to logic 0 before the allocation calculation. this automatically ensures that these sub-bands do not get any bits allocated. the following table shows the sub-bands affected and the resulting frequency range. the transfer of either 8-bits or 16-bits is permitted for the transfer of status information. when only 8-bits are transferred, these will always form the first byte and may be used in checking the ready-to-receive bit.
august 1993 19 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 table 11 frequency examples. bit rate f s sub-bands set to 0 @ frequency 256 kbit/s 48 khz 29, 30, 31 > 21750 hz 192 kbit/s 48 khz 20, 21, ... , 30, 31 > 15000 44.1 khz 22, 23, ... , 30, 31 > 15159 128 kbit/s 48 khz 12, 13, ... , 30, 31 > 9000 44.1 khz 13, 14, ... , 30, 31 > 8957 32 khz 20, 21, ... , 30, 31 >10000 fig.15 microcontroller to saa2521 timing. t le > 210 ns minimum low time ltena prior to transfer t s1 > 50 ns set-up time ltcnt0, 1 before ltena high t h1 > 210 ns hold time ltcnt0, 1 after ltena high t s2 > 210 ns set-up time ltena before ltclk low t h2 > 210 ns hold time ltena after ltclk high t lc > 210 ns minimum low time ltclk t hc > 210 ns minimum high time ltclk t s3 > 210 ns set-up time ltdata before ltclk high t h3 > 50 ns hold time ltdata after ltclk high t s4 > 210 ns set-up time ltclk before ltena high mea658 - 2 ltena ltclk ltdata bit : t le t su1 t h1 t su4 t h2 t ch t cl t su2 t t su3 h3 01 ltcnt0/1
august 1993 20 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 t w1 > 550 ns minimum time between two 8-bit transfers mbc135 - 1 ltena ltcnt0/1 ltclk ltena must remain high w1 t fig.16 16-bit transfers. mea657 - 2 ltena ltcnt0/1 ltclk ltdata bit : t le t su1 t h1 t su4 t h2 t ch t cl t su2 t t d1 d2 01 t h5 t h6 fig.17 saa2521 to microcontroller timing. t le > 210 ns minimum low time ltena prior to transfer t s1 > 50 ns set-up time ltcnt0, 1 before ltena high t h1 > 210 ns hold time ltcnt0, 1 after ltena high t s2 > 210 ns set-up time ltena before ltclk low t h2 > 210 ns hold time ltena after ltclk high t lc > 210 ns minimum low time ltclk t hc > 210 ns minimum high time ltclk t d1 < 385 ns maximum delay ltdata after ltena high t d2 < 385 ns maximum delay ltdata after ltclk high t h5 > 145 ns hold time ltdata after ltclk high t s4 > 210 ns set-up time ltclk before ltena high t h6 > 0 ns hold time ltdata after ltena low
august 1993 21 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 t w2 > 550 ns minimum time between two 8-bit transfers mbc137 ltena ltcnt0/1 ltclk ltena must remain high w2 t fig.18 16-bit transfers. mbc138 - 2 ltenc ltclkc ltdatac bit : t le t su1 t su4 t h2 t ch t cl t su2 t t su3 h3 01 ltcnt0(c)/1(c) fig.19 saa2521 to saa2520 timing. t le > 400 ns minimum low time ltena prior to transfer t s1 > 400 ns set-up time ltcnt0, 1c before ltenc high t s2 > 200 ns set-up time ltenc before ltclkc low t h2 > 400 ns hold time ltenc after ltclk high t lc > 210 ns minimum low time ltclkc t hc > 210 ns minimum high time ltclkc t s3 > 210 ns set-up time ltdatac before ltclkc high t h3 > 160 ns hold time ltdatac after ltclkc high t s4 > 900 ns set-up time ltclkc before ltenc high
august 1993 22 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 mbc139 ltenc ltclkc ltenc must remain high w2 t ltcnt0(c)/1(c) fig.20 16-bit transfers. t w2 > 600 ns minimum time between two 8-bit transfers mbc140 - 2 ltenc ltclkc ltdatac bit : t le t su1 t su4 t h2 t ch t cl t su2 t t d1 d2 01 t h5 t h6 ltcnt0(c)/1(c) fig.21 saa2520 to saa2521 timing. t le > 400 ns minimum low time ltenc prior to transfer t s1 > 400 ns set-up time ltcnt0, 1c before ltenc high t s2 > 200 ns set-up time ltenc before ltclkc low t h2 > 400 ns hold time ltenc after ltclkc high t lc > 210 ns minimum low time ltclkc t hc > 210 ns minimum high time ltclkc t d1 < 300 ns maximum delay ltdatac after ltenc high t d2 < 300 ns maximum delay ltdatac after ltclkc high t s4 > 900 ns set-up time ltclkc before ltenc high t h5 > 160 ns hold time after ltclkcc high t h6 > 0 ns hold time ltdatac after ltenc low
august 1993 23 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 fig.22 16-bit transfers. t w1 > 600 ns minimum time between two 8-bit transfers mbc141 ltenc ltclkc ltenc must remain high w2 t ltcnt0(c)/1(c) limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. input voltage should not exceed 6.5 v unless otherwise specified. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. symbol parameter min. max. unit v dd supply voltage - 0.5 6.5 v v i input voltage (note 1) - 0.5 v dd + 0.5 v i dd supply current - 100 ma i i input current - 10 ma i o output current - 40 ma p tot total power dissipation - 550 mw t stg storage temperature - 55 + 150 c t amb operating ambient temperature - 40 + 85 c v es1 electrostatic handling (note 2) - 1500 1500 v v es2 electrostatic handling (note 3) - 70 70 v
august 1993 24 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 dc characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to 85 c; unless otherwise speci?ed. note 1. maximum load current for ltdata, ltcnt1c, ltcnt0c, ltenc, ltclkc, test1, test2, fdac, fdaf = 2 ma; for ltdatac = 3 ma. symbol parameter conditions min. typ. max. unit supply v dd supply voltage range 3.8 5 5.5 v i dd operating current v dd = 3.8 v - 15 30 ma i dd operating current v dd = 5 v - 25 50 ma i pwrdwn stand-by current in power-down mode - 100 -m a inputs v il low level input voltage 0 - 0.3 v dd v v ih high level input voltage 0.7 v dd - v dd v i i input current -- 10 m a outputs v ol low level output voltage note 1 -- 0.4 v v oh high level output voltage note 1 v dd - 0.5 -- v 3-state outputs i oz off state current v i = 0 to 5.5 v -- 10 m a
august 1993 25 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 ac characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to 85 c. notes 1. inputs fsync, sws, ltcnt1, ltcnt0, ltena, ltclk, ltdata, ltdatac 2. inputs fdaf, fdac, scl, sws 3. outputs ltdata, ltdatac, ltcnt1c, ltcnt0c, ltenc, ltclk 4. outputs fdaf, fdac symbol parameter conditions min. typ. max. unit clock clk24 f s frequency 23 24.576 26 mhz clock f s 256 f s frequency f s = 48 khz -- 13 mhz inputs fsync, sws, ltcnt1, ltcnt0, ltena, ltclk, ltdata, ltdatac, fdaf, fdac, scl, sws c i input capacitance -- 10 pf i nput set - up time t su set-up time of inputs related to clk24 rising edge note 1 15 -- ns t su set-up time of inputs related to 256f s rising edge note 2 15 -- ns i nput hold time t hd hold time of inputs related to clk24 rising edge note 1 20 -- ns t hd hold time of inputs related to 256f s rising edge note 2 10 -- ns outputs ltdata, ltdatac, ltcnt1c, ltcnt0c, ltenc, ltclkc, fdaf, fdac c o output capacitance -- 10 pf t d output delay time related to clk24 rising edge c l = 25 pf; note 3 -- 45 ns t d output delay time related to 256f s rising edge c l = 25 pf; note 4 -- 30 ns 3-state outputs t phz disable time high-to-z c l = 25 pf -- 65 ns t plz disable time low-to-z c l = 25 pf -- 65 ns t pzh enable time z-to-high c l = 25 pf -- 65 ns t pzl enable time z-to-low c l = 25 pf -- 65 ns
august 1993 26 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 19.2 18.2 2.4 1.8 7 0 o o 0.15 2.35 0.1 0.3 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2.0 1.2 sot205-1 95-02-04 97-08-01 d (1) (1) (1) 14.1 13.9 h d 19.2 18.2 e z 2.4 1.8 d b p e q e a 1 a l p detail x l (a ) 3 b 11 y c d h b p e h a 2 v m b d z d a z e e v m a x 1 44 34 33 23 22 12 133e01a pin 1 index w m w m 0 5 10 mm scale qfp44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm sot205-1 a max. 2.60
august 1993 27 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
august 1993 28 philips semiconductors preliminary speci?cation masking threshold processor for mpeg layer 1 audio compression applications saa2521 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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